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preliminary data this is preliminary information on a new product now in deve lopment or undergoing evaluation. details are subject to change without notice. august 2010 doc id 17726 rev 1 1/32 32 LPS001D mems pressure sensor: 300 - 1100 mbar absolute digital output barometer features piezoresistive pressure sensor very low power consumption 300 -1100 mbar absolute pressure range 0.1 mbar resolution embedded offset and span temperature compensation embedded 16-bit adc spi and i 2 c interfaces supply voltage: 2.2 v to 3.6 v 1.8 v compatible ios high shock survivability (10000 g ) small, thin package ecopack ? lead-free compliant applications altimeter and barometer for portable devices gps applications weather station equipment sport watches description the LPS001D is an ultra-compact absolute piezoresistive pressure sensor. it includes a monolithic sensing element and an ic interface capable of taking information from the sensing element and providing a digital signal to external applications. the sensing element cons ists of a suspended membrane within a single monosilicon substrate, manufactured using a dedicated process developed by stmicroelectronics called ?vensens?. the vensens process allows the construction of a monosilicon membrane above an air cavity with a controlled gap and defined pressure. the membrane is very small compared to traditional silicon micromachined membranes. membrane breakage is prevented by intrinsic mechanical stoppers. the ic interface is manufactured using a standard cmos process that allows a high level of integration, to design a dedicated circuit which is trimmed to better match the sensing element characteristics. the LPS001D is available in a small plastic land grid array (lga) package, and is guaranteed to operate over a temperature range extending from -40 c to +85 c. the package is holed to allow external pressure to reach the sensing element. hlga 5x5 16l table 1. device summary order code temperature range [c] package packing LPS001Dl -40 to +85 hlga 5x5 16l tray LPS001Dltr -40 to +85 hlga 5x5 16l tape and reel www.st.com datasheet.in
contents LPS001D 2/32 doc id 17726 rev 1 contents 1 block diagram and pin informatio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 sensing element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.2 ic interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3 factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1 soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6 digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.1 i2c serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.1.1 i 2 c operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.2 spi bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.2.1 spi read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.2.2 spi write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.2.3 spi read in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7 register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.1 who_am_i (0fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.2 ctrl_reg1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.3 ctrl_reg2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.4 ctrl_reg3 [interrupt ctrl register] (22h) . . . . . . . . . . . . . . . . . . . . . . 23 8.5 status_reg (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.6 press_out_l (28h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 datasheet.in
LPS001D contents doc id 17726 rev 1 3/32 8.7 press_out_h (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.8 temp_out_l (2ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.9 temp_out_h (2bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.10 delta_p_l (2ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.11 delta_p_h (2dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.12 ref_p_l (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.13 ref_p_h (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.14 ths_p_l (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.15 ths_p_h (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.16 interrupt_cfg (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.17 int_source (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.18 int_ack (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 datasheet.in
list of tables LPS001D 4/32 doc id 17726 rev 1 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 3. mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 4. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 5. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 6. serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 7. serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 8. sad+read/write patterns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 9. transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 10. transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 11. transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 16 table 12. transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 16 table 13. register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 14. who_am_i (0fh) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 16. ctrl_reg1 (20h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 17. output data rate bit configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 18. ctrl_reg2 (21h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 19. ctrl_reg2 (21h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 20. ctrl_reg3 [interrupt ctrl register] (22h) register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 21. ctrl_reg3 [interrupt ctrl register] (22h) register description . . . . . . . . . . . . . . . . . . . 23 table 22. data signal on int1(2) pad control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 23. status_reg (27h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 24. status_reg (27h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 25. press_out_l (28h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 26. press_out_l (28h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 27. press_out_h (29h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 28. press_out_h (29h) regist er description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 29. temp_out_l (2ah) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 30. temp_out_l (2ah) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 31. temp_out_h (2bh) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 32. temp_out_h (2bh) register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 33. delta_p_l (2ch) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 34. delta_p_l (2ch) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 35. delta_p_h (2dh) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 36. delta_p_h (2dh) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 37. ref_p_l (30h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 38. ref_p_l (30h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 39. ref_p_h (31h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 40. ref_p_h (31h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 41. ths_p_l (32h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 42. ths_p_l (32h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 43. ths_p_h (33h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 44. ths_p_h (33h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 45. interrupt_cfg (34h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 46. interrupt_cfg (34h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 47. int_source (35h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 48. int_source (35h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 49. int_ack (36h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 50. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 datasheet.in
LPS001D list of figures doc id 17726 rev 1 5/32 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. interrupt generation block and output pressure data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 4. LPS001D electrical connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 5. read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 6. spi read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 7. multiple bytes spi read protocol (2 byte example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 8. spi write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 9. multiple bytes spi write protocol (2 byte example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 10. spi read protocol in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 11. hlga 5x5 16l: mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . 30 datasheet.in
block diagram and pin information LPS001D 6/32 doc id 17726 rev 1 1 block diagram and pin information figure 1. block diagram figure 2. pin connection table 2. pin description pin # pin name function 1cs spi enable i 2 c/spi mode selection (logic 1: i 2 c mode; logic 0: spi enabled) 2 scl/spc i 2 c serial clock (scl) spi serial port clock (spc) p mux 16 bit ? adc d s p for low noi s e digital filter temperature compen s ation analog front end i 2 c c s s en s or bia s temperature s en s or voltage and current bia s clock timing s pi s cl/ s pc s da/ s do/ s di s a0/ s do + vup vdown vout r s r s r s r s s en s ing element and am07299v1 re s erved bottom view vdd vdd vdd_io gnd re s erved re s erved gnd re s erved int2 int1 s a0/ s do s da/ s di/ s do gnd s cl/ s pc c s pin 1 indic a tor 1 1 5 6 16 8 9 1 3 14 pin 1 indic a tor am07300v1 datasheet.in
LPS001D block diagram and pin information doc id 17726 rev 1 7/32 3 gnd 0 v supply 4 sda/ sdi/ sdo i 2 c serial data (sda) spi serial data input (sdi) 3-wire interface serial data output (sdo) 5sa0/sdo i 2 c less significant bit of de vice slave address (sa0) spi serial data output 6 int1 interrupt 1 (or data ready) 7 int2 interrupt 2 (or data ready) 8 reserved leave unconnected 9 gnd 0 v supply 10 reserved connect to gnd 11 reserved connect to gnd 12 gnd 0 v supply 13 vdd_io power supply for i/o pads 14 reserved connect to vdd 15 vdd power supply 16 vdd power supply table 2. pin description (continued) pin # pin name function datasheet.in
mechanical and electrical specifications LPS001D 8/32 doc id 17726 rev 1 2 mechanical and electrical specifications 2.1 mechanical characteristics vdd = 2.5 v, t = 25 c, unless otherwise noted. table 3. mechanical characteristics symbol parameter test condition min. typ. (1) max. unit pop operating pressure range 300 1100 mbar res (2) resolution in normal mode p = 1013 mbar; t = 25 c 0.1 mbar resolution in low-power mode p = 1013 mbar; t = 25 c 0.13 acc accuracy p = 300 to 1100 mbar; t = 25 c 20 mbar acct accuracy over temperature range p = 1013 mbar; t = 25 c to +60 c 1.5 (3) mbar p = 1013 mbar; -40 c < t < 25 c or 60 c < t < 85 c 0.5 mbar/c pso pressure sensitivity 16 lsb/mbar tso temperature sensitivity 64 lsb/c 1. typical specificat ions are not guaranteed. 2. parameter given as standard deviation value. 3. overall pressure drift in the range from 25 c to 60 c. datasheet.in
LPS001D mechanical and electrical specifications doc id 17726 rev 1 9/32 2.2 electrical characteristics vdd = 2.5 v, t = 25 c, unless otherwise noted. table 4. electrical characteristics symbol parameter test condition min. typ. (1) max. unit vdd supply voltage 2.2 3.6 v vdd_io i/o supply voltage 1.7 vdd+0.1 v idd supply current continous mode odr p = 7 hz odr t = 1 hz 190 a during conversion 400 iddlpr supply current in low-power mode continous mode odr p = 7 hz odr t = 1 hz 120 a iddpdn supply current in power-down mode 5a odr p pressure output data rate (2) 712.5hz odr t temperature output data rate (2) 1712.5hz top operating temperature range -40 +85 c 1. typical specificat ions are not guaranteed. 2. for pressure and temperature output data rate configurations, refer to table 17 . datasheet.in
absolute maximum ratings LPS001D 10/32 doc id 17726 rev 1 3 absolute maximum ratings stresses above those listed as ?absolute ma ximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 5. absolute maximum ratings symbol ratings maximum value unit vdd supply voltage -0.3 to 6 v vdd_io i/o pins supply voltage -0.3 to 6 v vin input voltage on any control pin -0.3 to vdd +0.3 v p overpressure 12 bar t stg storage temperature range -40 to +125 c this is a mechanical shock-sensitive device. improper handling can cause permanent damage to the part. this is an esd sensitive device. improper handling can cause permanent damage to the part. datasheet.in
LPS001D functionality doc id 17726 rev 1 11/32 4 functionality the LPS001D is a high-resolution, digital-output pressure sensor packaged in an lga holed package. the complete device includes a sensing element based on a piezoresistive wheatstone bridge approach, and an ic interface capable of providing information from the sensing element to external applications as a digital signal. 4.1 sensing element an st proprietary process is used to obtain a monosilic on -sized membrane for mems pressure sensors, without requiring substrate-to-substrate bonding. when pressure is applied, membrane deflection induces an imbalance in the wheatstone bridge piezoresistors, whose output signal is converted by the ic interface. intrinsic mechanical stoppers prevent breakage in case of pressure overstress, ensuring measurement repeatability. the pressure inside the buried cavity under the membrane is constant and controlled by process parameters. to be compatible with traditio nal packaging technologies, a s ilicon holed cap is placed on top of the sensing element. during the moulding phase, this opening is covered by dedicated protection to avoid membrane blocking. the package design leaves the holed cap exposed, allowing ambient pressure to reach the sensing element. 4.2 ic interface figure 3. interrupt generation block and output pressure data. reference pre ss ure - -1 + - ref_p_h & ref_p_l + output pre ss ure pre ss _out_h & pre ss _out_l delta pre ss ure delta_p_h & delta_p_l pre ss ure thre s hold th s _p_h & th s _p_l low pre ss ure int_ s ource (pl) + - interrupt hi g h pre ss ure int_ s ource (ph) interrupt reference pre ss pre ss thre s hold pre ss thre s hold hi g h pre ss int low pre ss int po s itive ne g ative am07 3 01v1 datasheet.in
functionality LPS001D 12/32 doc id 17726 rev 1 the complete measurement chain consists of a low-noise capacitive amplifier, which converts the resistive imbalance of the mems sensor into an analog voltage signal, and an analog-to-digital converter, which translates the signal produced into a digital bitstream. the converter is coupled with a dedicated reco nstruction filter which removes the high frequency components of the quantization noise and provides low rate and high resolution digital words. the pressure data can be accessed through an i 2 c/spi interface, thus making the device particularly suitable for direct interfacing with a microcontroller. the device features two fully-programmable interrupt sources ( int1 and int2 ) which may be configured to trigger different pressure events. figure 3 shows the block diagram of the interrupt generation block and output pressure data. the device may also be configured to generate, through interrupt pins, a data ready signal ( drdy ) which indicates when new measured pressure data is available, thus simplifying data synchronization in digital systems. 4.3 factory calibration the ic interface is factory-calibrated at two temperatures and two pressure levels for sensitivity and accuracy. the trimming values are stored inside the device using a non-volatile structure. each time the device is turned on, the trimming parameters are downloaded into the registers to be employed during normal operation. this allo ws the user to employ the device without requiring further calibration. datasheet.in
LPS001D application hints doc id 17726 rev 1 13/32 5 application hints figure 4. LPS001D electrical connection the device core is supplied through the vdd line while the i/o pads are supplied through the vdd_io line. power supply decoupling capacitors (100 nf ceramic, 10 f aluminum) should be placed as near as possible to the supply pad of the device (common design practice). all the voltage and ground supplies must be present at the same time to obtain proper behavior of the ic (refer to figure 4 ). it is possible to remo ve the vdd while maintaining vdd_io without blocking the communication busses. in this condition the measurement chain is powered off. the functionality of the device and the measured data outputs are selectable and accessible through the i 2 c/spi interface.when using the i 2 c, cs must be tied high. the functions and the threshold of the two interrupt pins (int 1 and int 2) can be completely programmed by the user though the i 2 c/spi interface. 5.1 soldering information the lga package is compliant with the ecopack ? standard. it is qualified for soldering heat resistance in accordance with jedec j-std-020c. leave ?pin 1 indicator? unconnected during soldering. pin 1 indic a tor 1 lp s 001d (top view) gnd 4 2 3 di g ital s i g nal s c s vdd gnd gnd 100nf 10 f 5 1 67 8 10 12 11 9 1 3 16 15 14 s cl/ s pc s da/ s di/ s do s a0/ s do int1 int2 gnd vdd_io am07 3 02v1 datasheet.in
digital interfaces LPS001D 14/32 doc id 17726 rev 1 6 digital interfaces the registers embedded in the LPS001D may be accessed through both the i 2 c and spi serial interfaces. the latter may be sw configured to operate either in 3-wire or 4-wire interface mode. the serial interfaces are mapped onto the same pads. to select/exploit the i 2 c interface, the cs line must be tied high (i.e connected to vdd_io). 6.1 i 2 c serial interface the LPS001D i 2 c is a bus slave. the i 2 c is employed to write the data into the registers whose content can also be read back. the relevant i 2 c terminology is provided in the table below: there are two signals associated with the i 2 c bus: the serial clock line (scl) and the serial data line (sda). the latter is a bidirectional line used for sending and receiving the data to/from the interface. both the lines are connected to vdd_io through a pull-up resistor embedded inside the LPS001D. when the bus is free, both the lines are high. the i 2 c interface is compliant wit h fast mode (400 khz) i 2 c standards, as well as normal mode. table 6. serial interface pin description pin name pin description cs spi enable i 2 c/spi mode selection (1: i 2 c mode; 0: spi enabled) scl/spc i 2 c serial clock (scl) spi serial port clock (spc) sda/sdi/sdo i 2 c serial data (sda) spi serial data input (sdi) 3-wire interface serial data output (sdo) sa0/sdo i 2 c less significant bit of device slave address (sa0) spi serial data output (sdo) table 7. serial interface pin description term description transmitter the device which sends data to the bus receiver the device which receives data from the bus master the device which initiates a transfer, g enerates clock signals and terminates a transfer slave the device addressed by the master datasheet.in
LPS001D digital interfaces doc id 17726 rev 1 15/32 6.1.1 i 2 c operation the transaction on the bus is started through a start (st) signal. a start condition is defined as a high to low transition on the data line while the scl line is held high. after this has been transmitted by the master, the bus is considered busy. the next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. when an address is sent, each device in the system compares the first seven bits after a start condition with its address. if they match, the device considers itself addressed by the master. the slave address (sad) associated with the LPS001D is 101110xb. the sdo pad can be used to modify the less significant bit of the de vice address. if the sdo pad is connected to the voltage supply, lsb is ?1? (address 1011101b). otherwise, if the sdo pad is connected to ground, the lsb value is ?0? (address 1011100b). this solution permits the connection and addressing of two different LPS001D devices to the same i 2 c lines. data transfer with acknowledge is mandatory. the transmitter must release the sda line during the acknowledge pulse. the receiver must then pull the data line low so that it remains stable low during the high period of the acknowledge clock pulse. a receiver which has been addressed is required to generate an acknowledge after each byte of data has been received. the i 2 c embedded in the LPS001D behaves as a slave device and the protocol which follows must be adhered to. after the start condition (st) a slave address is sent (sad + r/w). once a slave acknowledge (sak) has been returned, an 8- bit sub-address is transmitted (sub): the 7 lsb represent the actual register address, while the msb enables address auto-increment. if the msb of the sub field is ?1?, the sub (register address) is automatically incremented to a llow multiple data read/write. the slave address is completed with a read/write bit. if the bit was ?1? (read), a repeated start (sr) condition must be issued after the two sub-address bytes; if the bit is ?0? (write) the master transmits to the slave with direction unchanged. table 8 explains how the sad+read/write bit pattern is composed, listing all the possible configurations. table 8. sad+read/write patterns command sad[6:1] sad[0] = sdo r/w sad+r/w read 101110 0 1 10111001 (39h) write 101110 0 0 10111000 (38h) read 101110 1 1 10111011 (3bh) write 101110 1 0 10111010 (3ah) table 9. transfer when master is writing one byte to slave master st sad + w sub data sp slave sak sak sak datasheet.in
digital interfaces LPS001D 16/32 doc id 17726 rev 1 data are transmitted in byte format (data). each data transfer contains 8 bits. the number of bytes transferred per transfer is unlimited. data is transferred with the most significant bit (msb) first. if a receiver cannot receive another complete byte of data until it has performed some other function, it can hold the clock line (scl) low to force the transmitter into a wait state. data transfer only continues when the receiver is ready for another byte and releases the data line. if a slave receiver does not acknowledge the slave address (i.e. it is not able to receive because it is performing some real-time function) the data line must be left high by the slave. the master can then abort the transfer. a low to high transition on the sda line while the scl line is high is defined as a stop condition. each data transfer must be terminated by the generation of a stop (sp) condition. in order to read multiple bytes, to increment the register address it is necessary to assert the most significant bit of the sub-address field. in other words, sub(7) must be equal to 1 while sub(6-0) represents the address of the first register to read. in the communication format presented, mak is master acknowledg e and nmak is no master acknowledge . 6.2 spi bus interface the LPS001D spi is a bus slave. the spi allows writing and reading of the registers of the device. the serial interface interacts with external applications with 4 wires: cs, spc, sdi and sdo. table 10. transfer when master is writing multiple bytes to slave master st sad + w sub data data sp slave sak sak sak sak table 11. transfer when master is receiving (reading) one byte of data from slave master st sad + w sub sr sad + r nmak sp slave sak sak sak data table 12. transfer when master is receiving (reading) multiple bytes of data from slave master st sad+w sub sr sad+r mak mak nmak sp slave sak sak sak data data data datasheet.in
LPS001D digital interfaces doc id 17726 rev 1 17/32 figure 5. read and write protocol cs is the serial port enable and is controlled by the spi master. it goes low at the start of the transmission and goes back high at the end. spc is the serial port clock and is controlled by the spi master. it is stopped high when cs is high (no transmission). sdi and sdo are respectively the serial port da ta input and output. these lines are driven at the falling edge of spc and should be captured at the rising edge of spc. both the read register and write register commands are completed in 16 clock pulses or in multiple of 8 in case of multiple byte read/w rite. bit duration is the time between two falling edges of spc. the first bit (bit 0) starts at t he first falling edge of spc after the falling edge of cs while the last bit (bit 15, bit 23, ...) starts at the last falling edge of spc just before the rising edge of cs. bit 0 : rw bit. when 0, the data di(7:0) is written into the device. when 1, the data do(7:0) from the device is read. in the latter case, the chip drives sdo at the start of bit 8. bit 1 : ms bit. when 0, the address remains unchanged in multiple read/write commands. when 1, the address is auto-incremented in multiple read/write commands. bit 2-7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data di(7:0) (write mode). this is the data that is written into the device (msb first). bit 8-15 : data do(7:0) (read mode). this is the data that is read from the device (msb first). in multiple read/write commands, further blocks of 8 clock periods are added. when the ms bit is 0, the address used to read/write data remains the same for every block. when the ms bit is 1, the address used to read/write data is incremented at every block. the function and the behavior of sdi and sdo remain unchanged. 6.2.1 spi read figure 6. spi read protocol cs spc sdi sdo rw ad5 ad4 ad3 ad2 ad1 ad0 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 ms cs spc sdi sdo rw do7 do6 do5 do4 do3 do2 do1 do0 ad5 ad4 ad3 ad2 ad1 ad0 ms datasheet.in
digital interfaces LPS001D 18/32 doc id 17726 rev 1 the spi read command is performed with 16 clock pulses. a multiple byte read command is performed by adding blocks of 8 clock pulses to the previous one. bit 0 : read bit. the value is 1. bit 1 : ms bit. when 0, do not increment the address; when 1, increment the address in multiple reading. bit 2-7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data do(7:0) (read mode). this is the data that is read from the device (msb first). bit 16-... : data do(...-8). further da ta in multiple byte reading. figure 7. multiple bytes spi read protocol (2 byte example) 6.2.2 spi write figure 8. spi write protocol the spi write command is performed with 16 clock pulses. the multiple byte write command is performed by adding blocks of 8 clock pulses to the previous one. bit 0 : write bit. the value is 0. bit 1 : ms bit. when 0, do not increment address; when 1, increment the address in multiple writing. bit 2 -7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data di(7:0) (write mode). this is the data that is written inside the device (msb first). bit 16-... : data di(...-8). further data in multiple byte writing. cs spc sdi sdo rw do7 do6 do5 do4 do3 do2 do1 do0 ad5 ad4 ad3 ad2 ad1 ad0 do15 do14 do13 do12 do11 do10 do9 do8 ms cs spc sdi rw di7 di6 di5 di4 di3 di2 di1 di0 ad5 ad4 ad3 ad2 ad1 ad0 ms datasheet.in
LPS001D digital interfaces doc id 17726 rev 1 19/32 figure 9. multiple bytes spi write protocol (2 byte example) 6.2.3 spi read in 3-wires mode 3-wires mode is entered by setting to 1 the bit sim (spi serial interface mode selection) in the internal control register. figure 10. spi read protocol in 3-wires mode the spi read command is performed with 16 clock pulses: bit 0 : read bit. the value is 1. bit 1 : ms bit. when 0, do not increment the address; when 1, increment the address in multiple reading. bit 2-7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data do(7:0) (read mode). this is the data that is read from the device (msb first). multiple read command is also available in 3-wires mode. cs spc sdi rw ad5 ad4 ad3 ad2 ad1 ad0 di7 di6 di5 di4 di3 di2 di1 di0 di15 di14 di13 di12 di11 di10 di9 di8 ms cs spc sdi/o rw do7 do6 do5 do4 do3 do2 do1 do0 ad5 ad4 ad3 ad2 ad1 ad0 ms datasheet.in
register mapping LPS001D 20/32 doc id 17726 rev 1 7 register mapping table 13 below provides a listing of the 8-bit registers embedded in the device, and the related addresses. . registers marked as reserved must not be changed. writing to those registers may cause permanent damage to the device. the content of the registers that are loaded at boot should not be changed. they contain the factory calibration values. their content is automatically restored when the device is powered up. table 13. register address map name type register address default comment hex binary reserved (do not modify) 00-0e reserved who_am_i r 0f 000 1111 10111010 dummy register reserved (do not modify) 10-1f reserved ctrl_reg1 rw 20 010 0000 00000000 ctrl_reg2 rw 21 010 0001 00000000 ctrl_reg3 rw 22 010 0010 00000000 reserved (do not modify) 23-26 reserved status_reg r 27 010 0111 00000000 press_out_l r 28 010 1000 output press_out_h r 29 010 1001 output temp_out_l r 2a 010 1010 output temp_out_h r 2b 010 1011 output delta_p_l r 2c 010 1100 output delta_p_h r 2d 010 1101 output reserved (do not modify) 2e-2f reserved ref_p_l rw 30 011 0000 00000000 ref_p_h rw 31 011 0001 00000000 ths_p_l rw 32 011 0010 00000000 ths_p_h rw 33 011 0011 00000000 interrupt_cfg rw 34 011 0100 00000000 int_source r 35 011 0101 output int_ack r 36 011 0110 dummy register reserved (do not modify) 37-3f reserved datasheet.in
LPS001D register description doc id 17726 rev 1 21/32 8 register description the device contains a set of registers which are used to control its behavior and to retrieve pressure and temperature data. the register address, made up of 7 bits, is used to identify them and to read/write the data through the serial interface. 8.1 who_am_i (0fh) device identification register. this read-only register contains the device i dentifier that, for the LPS001D, is set to bah. 8.2 ctrl_reg1 (20h) the lowpwr bit is used to modify resolution and power consumption. in default mode this bit is ?0? and processing is done in normal mode with high resolution. when this bit is set to ?1? the device operates in low-po wer mode with lower resolution. table 14. who_am_i (0fh) register 10111010 table 15. ctrl_reg1 (20h) register lowpwr pd odr1 odr0 diff_en bdu ble sim table 16. ctrl_reg1 (20h) register description lowpow low power functionality. default value: 0 (0: normal mode; 1: low-power activated) pd power down control. default value: 0 (0: power-down mode; 1: active mode) odr1 odr0 output data rate selection. default value: 00 (see table 17 ) diff_en interrupt circuit enable. default value: 0 (0: interrupt generation disabled; 1: interrupt circuit enabled) bdu block data update. default value: 0 (0: continuous update; 1: output registers not updated until msb and lsb reading) ble big/little endian selection. default value: 0 (0: little endian; 1: big endian) sim spi serial interface mode selection. default value: 0 (0: 4-wire interface; 1: 3-wire interface) datasheet.in
register description LPS001D 22/32 doc id 17726 rev 1 the pd bit is used to turn on the device. the device is in power-down mode when pd = ?0? (default value after boot). the device is active when pd is set to ?1?. the odr1 - odr0 bits change the output data rates of pressure and temperature samples. the default value is ?00?, which corresponds to a data rate of 7 hz for pressure output and 1 hz for temperature output. odr1 and odr2 bits can be configured as described in table 17 . the diff_en bit is used to enable the circuitry for the computing of delta pressure output, delta_p. in default mode (diff_en = ?0?), this circuitry is turned off. it is recommended to turn on the circuitry only after the configuration of ref_p_l, ref_p_h, ths_p_l and ths_p_h registers, which are used by the circuitry. the bdu bit is used to inhibit the update of output registers between the reading of upper and lower register parts. in default mode (bdu = ?0?), the lower and upper register parts are updated continuously. if it is not certain that it can read faster than the output data rate, it is recommended to set the bdu bit to ?1?. in this way, after the reading of the lower (upper) register part, the content of that output register is not updated until the upper (lower) part is read also. this feature prevents reading lsb and msb related to different samples. the ble bit is used to select big endian or little en dian representation for output registers. in the big endian representation, msb values are located in press_out_l (pressure), temp_out_l (temperature) and delta_p_l (delta pressure), while lsb values are located in press_out_h, temp_out_h and delt a_p_h. in little endian representation, the order is inverted (refer to data register description for more details). the sim bit selects the spi serial interface mode. when sim is ?0? (defau lt value), the 4-wire interface mode is selected and data coming from the device are sent to pin #4 (sdo). in 3- wire interface mode, output data are sent to pin #5 (sdi/sdo). 8.3 ctrl_reg2 (21h) table 17. output data rate bit configurations odr1 (1) 1. ?10? bit configuration is not allowed and may cause incorrec t device functionality. odr0 (1) pressure output data rate te mperature output data rate 0 0 7 hz 1 hz 0 1 7 hz 7 hz 1 1 12.5 hz 12.5 hz table 18. ctrl_reg2 (21h) register bootxxxxxx0 (1) 1. bit to be kept to ?0? for correct device functionality table 19. ctrl_reg2 (21h) register description boot reboot memory content. default value: 0 (0: normal mode; 1: reboot memory content) datasheet.in
LPS001D register description doc id 17726 rev 1 23/32 the boot bit is used to refresh the content of internal registers stored in the flash memory block. at device power-up, the content of the flash memory block is transferred to the internal registers related to trimming functions, to permit good behavior of the device. if for any reason the content of the trimming registers was changed, it is sufficient to use this bit to restore the correct values. when the boot bit is set to ?1?, the content of the internal flash is copied within the corresponding internal registers and is used to calibrate the device. these values are factory trimmed and are different for every device. they permit good behavior of the device and normally do not need to be changed. at the end of the boot process, the boot bit is set again to ?0?. boot bit takes effect after one odr clock cycle. 8.4 ctrl_reg3 [interrupt ctrl register] (22h) table 20. ctrl_reg3 [interrupt ctrl register] (22h) register h_l active pp_od int2_cfg3 int2_cfg2 int 2_cfg1 int1_cfg3 int 1_cfg2 int1_cfg1 table 21. ctrl_reg3 [interrupt ctrl register] (22h) register description h_l active interrupt active hi gh, low. default value: 0 (0: active high; 1: active low) pp_od push-pull/open drain selection on interrupt pads. default value: 0 (0: push-pull; 1: open drain) int2_cfg3 int2_cfg2 int2_cfg1 data signal on int2 pad control bits. default value: 000 (see table 22 ) int1_cfg3 int1_cfg2 int1_cfg1 data signal on int1 pad control bits. default value: 000 (see table 22 ) table 22. data signal on int1(2) pad control bits int1(2)_cfg3 (1) 1. these are the allowed bit configurations. int1(2)_cfg2 (1) int1(2)_cfg1 (1) int1(2) pad 0 0 0 gnd 0 0 1 pressure high (p_high) 0 1 0 pressure low (p_low) 0 1 1 p_low or p_high 1 0 0 pressure data ready (drdy) 111 tri-state datasheet.in
register description LPS001D 24/32 doc id 17726 rev 1 8.5 status_reg (27h) the content of this register is updated every odr cycle, regardless of the bdu value in ctrl_reg1. p_da is set to ?1? whenever a ne w pressure sample is availabl e. p_da is cleared anytime press_out_h (29h) re gister is read. t_da is set to ?1? whenever a new temperature samp le is available. t_da is cleared anytime temp_out_h (2bh) register is read. the p_or bit is set to ?1? whenever new pressure data is available and p_da was set in the previous odr cycle and not cleared. p_or is cleared anytime press_out_h (29h) register is read. t_or is set to ?1? whenever new temperature data is available and t_da was set in the previous odr cycle and not cleared. t_or is cleared anytime temp_out_h (2bh) register is read. 8.6 press_out_l (28h) table 23. status_reg (27h) register 0 0 p_or t_or 0 0 p_da t_da table 24. status_reg (27h) register description p_or pressure data overrun. default value: 0 (0: no overrun has occurred; 1: new data for pressure has overwritten the previous data) t_or temperature data overrun. default value: 0 (0: no overrun has occurred; 1: a new data for temperature has overwritten the previous data) p_da pressure data available. default value: 0 (0: new data for pressure is not yet available; 1: new data for pressure is available) t_da temperature data available. default value: 0 (0: new data for temperature is not yet available; 1: new data for temperature is available) table 25. press_out_ l (28h) register pout7 pout6 pout5 pout4 pout3 pout2 pout1 pout0 table 26. press_out_l (28h ) register description pout7 - pout0 pressure data lsb (when ble bit in ctrl_reg1 is set to ?0?, little endian) datasheet.in
LPS001D register description doc id 17726 rev 1 25/32 pressure data are expressed as absolute values. values exceeding the operating pressure range (see table 3 ) are clipped. in big endian mode (ble bit in ctrl_reg1 set to ?1?), the content of this register is the msb pressure data. 8.7 press_out_h (29h) in big endian mode (ble bit in ctrl_reg1 set to ?1?) the content of this register is the lsb pressure data. 8.8 temp_out_l (2ah) temperature data are expressed as 2?s complement numbers. in big endian mode (ble bit in ctrl_reg1 set to ?1?) the content of this register is the msb temperature data. 8.9 temp_out_h (2bh) table 27. press_out_h (29h) register pout15 pout14 pout13 pout12 pout11 pout10 pout9 pout8 table 28. press_out_h (29h ) register description pout15 - pout8 pressure data msb (when ble bit in ctrl_reg1 is set to ?0?) table 29. temp_out_l (2ah) register tout7 tout6 tout5 tout4 tout3 tout2 tout1 tout0 table 30. temp_out_l (2ah) register description tout7 - tout0 temperature data lsb (when ble bit in ctrl_reg1 register is set to ?0?, little endian) table 31. temp_out_h (2bh) register tout15 tout14 tout13 tout12 tout11 tout10 tout9 tout8 datasheet.in
register description LPS001D 26/32 doc id 17726 rev 1 temperature data are expressed as 2?s complement numbers. in big endian mode (ble bit in ctrl_reg1 set to ?1?) the content of this register is the lsb temperature data. 8.10 delta_p_l (2ch) delta_p registers store a delta pressure representing the difference between a constant reference value, ref_p registers, and the actual pressure measured, press_out registers. in big endian mode (ble bit in ctrl_reg1 set to ?1?) the content of this register is the msb delta pressure data. 8.11 delta_p_h (2dh) in big endian mode (ble bit in ctrl_reg1 set to ?1?) the content of this register is the lsb delta pressure data. 8.12 ref_p_l (30h) table 32. temp_out_h (2bh) register description tout8 - tout15 temperature data msb (when ble bit in ctrl_reg1 register is set to ?0?) table 33. delta_p_l (2ch) register dp7 dp6 dp5 dp4 dp3 dp2 dp1 dp0 table 34. delta_p_l (2ch) register description dp7 - dp0 delta pressure data lsb (when ble bit in ctrl_reg1 register is set to ?0?) table 35. delta_p_h (2dh) register dp15 dp14 dp13 dp12 dp11 dp10 dp9 dp8 table 36. delta_p_h (2dh) register description dp15 - dp8 delta pressure data msb (when ble bit in ctrl_reg1 register is set to ?0?). table 37. ref_p_l (30h) register refl7 refl6 refl5 refl4 refl3 refl2 refl1 refl0 datasheet.in
LPS001D register description doc id 17726 rev 1 27/32 this register contains the lower part of the reference pressure for computing of delta pressure. full value is ref_p_h & ref_p_l and is represented as an unsigned number. 8.13 ref_p_h (31h) this register contains the higher part of the reference pressure for computing of delta pressure. full value is ref_p_h & ref_p_l and is represented as an unsigned number. 8.14 ths_p_l (32h) this register contains the low part of the threshold value for pressure interrupt generation. the complete threshold value is given by ths_p_h & ths_p_l and is expressed as an unsigned number. 8.15 ths_p_h (33h) table 38. ref_p_l (30h) register description refl7 - refl0 reference pressure lsb data. default value: 00h. table 39. ref_p_h (31h) register refl15 refl14 refl13 refl12 refl11 refl10 refl9 refl8 table 40. ref_p_h (31h) register description refl15 - refl8 reference pressure msb data. default value: 00h. table 41. ths_p_l (32h) register ths7 ths6 ths5 ths4 ths3 ths2 ths1 ths0 table 42. ths_p_l (32h) register description ths7 - ths0 threshold pressure lsb. default value: 00h. table 43. ths_p_h (33h) register ths15 ths14 ths13 ths12 ths11 ths10 ths9 ths8 datasheet.in
register description LPS001D 28/32 doc id 17726 rev 1 this register contains the high part of the threshold value for pressure interrupt generation. the complete threshold value is given by ths_p_h & ths_p_l and is expressed as an unsigned number. 8.16 interrupt_cfg (34h) interrupt configuration register. 8.17 int_source (35h) interrupt source register. int_ source register is cleared by reading the int_ack register. table 44. ths_p_h (33h) register description ths15 - ths8 threshold pressure msb. default value: 00h. table 45. interrupt_cfg (34h) register x x x x x lir pl_e ph_e table 46. interrupt_cfg (34h) register description lir latch interrupt request into int_source register. default value: 0. (0: interrupt request not latched; 1: interrupt request latched) pl_e enable interrupt generation on delta pressure low event. default value: 0. (0: disable interrupt request; 1: enable interrupt request on measured delt a pressure value lower than preset threshold) ph_e enable interrupt generation on delta pressure high event. default value: 0 (0: disable interrupt request; 1:enable interrupt request on measured delta pr essure value higher than preset threshold) table 47. int_source (35h) register 00000iaplph table 48. int_source (35h) register description ia interrupt active. (0: no interrupt has been generated; 1: one or more interrupt events have been generated). pl delta pressure low. (0: no interrupt has been generated; 1: low delta pressure event has occurred). ph delta pressure high. (0: no interrupt has been generated; 1: high delta pressure event has occurred). datasheet.in
LPS001D register description doc id 17726 rev 1 29/32 8.18 int_ack (36h) dummy register. if the lir bit in the interrupt_cfg register is set to ?1?, a reading at this address clears the int_source register. read data are not significant. table 49. int_ack (36h) register xxxxxxxx datasheet.in
package information LPS001D 30/32 doc id 17726 rev 1 9 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack is an st trademark. figure 11. hlga 5x5 16l: mechanical data and package dimensions a1 1 a2 0.700 a 3 0.200 d1 4. 8 50 5.000 5.150 d2 0.100 d 3 0 d 0.200 e1 4. 8 50 5.000 5.150 e2 0.100 e 3 1.5 3 0 l1 1.600 l2 3 .200 m 0.100 n1 0. 8 00 n2 1.600 p1 2.095 p2 2.202 t1 0. 8 00 t2 0.500 k 0.050 hlga 5x5 16l land grid array packa g e 79 8 91 3 6_b dimen s ion s mm ref. min. typ. m a x. o u tline a nd mech a nic a l d a t a datasheet.in
LPS001D revision history doc id 17726 rev 1 31/32 10 revision history table 50. document revision history date revision changes 17-aug-2010 1 first release. datasheet.in
LPS001D 32/32 doc id 17726 rev 1 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2010 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com datasheet.in

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